HAL XSPI constants migration

This section provides information about the HAL XSPI constants migration .

Note

All constants are migrated using the following concept:

Replace Finite Parameter Defines (Including PPP Instances) with Enum Types at HAL Levels.

HAL XSPI address width

HAL1	HAL2
#define HAL_XSPI_ADDRESS_8_BITS #define HAL_XSPI_ADDRESS_16_BITS #define HAL_XSPI_ADDRESS_24_BITS #define HAL_XSPI_ADDRESS_32_BITS	typedef enum { HAL_XSPI_ADDR_8BIT HAL_XSPI_ADDR_16BIT HAL_XSPI_ADDR_24BIT HAL_XSPI_ADDR_32BIT } hal_xspi_addr_width_t;

---

HAL XSPI address mode

HAL1	HAL2
#define HAL_XSPI_ADDRESS_NONE #define HAL_XSPI_ADDRESS_1_LINE #define HAL_XSPI_ADDRESS_2_LINES #define HAL_XSPI_ADDRESS_4_LINES #define HAL_XSPI_ADDRESS_8_LINES	typedef enum { HAL_XSPI_ADDR_NONE HAL_XSPI_ADDR_1LINE HAL_XSPI_ADDR_2LINES HAL_XSPI_ADDR_4LINES HAL_XSPI_ADDR_8LINES } hal_xspi_addr_mode_t;

---

HAL XSPI address DTR mode

HAL1	HAL2
#define HAL_XSPI_ADDRESS_DTR_DISABLE #define HAL_XSPI_ADDRESS_DTR_ENABLE	typedef enum { HAL_XSPI_ADDR_DTR_DISABLED HAL_XSPI_ADDR_DTR_ENABLED } hal_xspi_addr_dtr_status_t;

---

HAL XSPI alternate bytes width

HAL1	HAL2
#define HAL_XSPI_ALT_BYTES_8_BITS #define HAL_XSPI_ALT_BYTES_16_BITS #define HAL_XSPI_ALT_BYTES_24_BITS #define HAL_XSPI_ALT_BYTES_32_BITS	typedef enum { HAL_XSPI_ALTERNATE_BYTES_8BIT HAL_XSPI_ALTERNATE_BYTES_16BIT HAL_XSPI_ALTERNATE_BYTES_24BIT HAL_XSPI_ALTERNATE_BYTES_32BIT } hal_xspi_alternate_bytes_width_t;

---

HAL XSPI alternate bytes mode

HAL1	HAL2
#define HAL_XSPI_ALT_BYTES_NONE #define HAL_XSPI_ALT_BYTES_1_LINE #define HAL_XSPI_ALT_BYTES_2_LINES #define HAL_XSPI_ALT_BYTES_4_LINES #define HAL_XSPI_ALT_BYTES_8_LINES	typedef enum { HAL_XSPI_ALTERNATE_BYTES_NONE HAL_XSPI_ALTERNATE_BYTES_1LINE HAL_XSPI_ALTERNATE_BYTES_2LINES HAL_XSPI_ALTERNATE_BYTES_4LINES HAL_XSPI_ALTERNATE_BYTES_8LINES } hal_xspi_alternate_bytes_mode_t;

---

HAL XSPI alternate bytes DTR mode

HAL1	HAL2
#define HAL_XSPI_ALT_BYTES_DTR_DISABLE #define HAL_XSPI_ALT_BYTES_DTR_ENABLE	typedef enum { HAL_XSPI_ALTERNATE_BYTES_DTR_DISABLED HAL_XSPI_ALTERNATE_BYTES_DTR_ENABLED } hal_xspi_alternate_bytes_dtr_status_t;

---

HAL XSPI automatic stop

HAL1	HAL2
#define HAL_XSPI_AUTOMATIC_STOP_DISABLE #define HAL_XSPI_AUTOMATIC_STOP_ENABLE	typedef enum { HAL_XSPI_AUTOMATIC_STOP_DISABLED HAL_XSPI_AUTOMATIC_STOP_ENABLED } hal_xspi_automatic_stop_status_t;

---

HAL XSPI chipselect boundary

HAL1

HAL2

#define HAL_XSPI_BONDARYOF_NONE #define HAL_XSPI_BONDARYOF_16B #define HAL_XSPI_BONDARYOF_32B #define HAL_XSPI_BONDARYOF_64B #define HAL_XSPI_BONDARYOF_128B #define HAL_XSPI_BONDARYOF_256B #define HAL_XSPI_BONDARYOF_512B #define HAL_XSPI_BONDARYOF_1KB #define HAL_XSPI_BONDARYOF_2KB #define HAL_XSPI_BONDARYOF_4KB #define HAL_XSPI_BONDARYOF_8KB #define HAL_XSPI_BONDARYOF_16KB #define HAL_XSPI_BONDARYOF_32KB #define HAL_XSPI_BONDARYOF_64KB #define HAL_XSPI_BONDARYOF_128KB #define HAL_XSPI_BONDARYOF_256KB #define HAL_XSPI_BONDARYOF_512KB #define HAL_XSPI_BONDARYOF_1MB #define HAL_XSPI_BONDARYOF_2MB #define HAL_XSPI_BONDARYOF_4MB #define HAL_XSPI_BONDARYOF_8MB #define HAL_XSPI_BONDARYOF_16MB #define HAL_XSPI_BONDARYOF_32MB #define HAL_XSPI_BONDARYOF_64MB #define HAL_XSPI_BONDARYOF_128MB #define HAL_XSPI_BONDARYOF_256MB #define HAL_XSPI_BONDARYOF_512MB #define HAL_XSPI_BONDARYOF_1GB #define HAL_XSPI_BONDARYOF_2GB #define HAL_XSPI_BONDARYOF_4GB #define HAL_XSPI_BONDARYOF_8GB #define HAL_XSPI_BONDARYOF_16GB

typedef enum { HAL_XSPI_CS_BOUNDARY_NONE HAL_XSPI_CS_BOUNDARY_16BIT HAL_XSPI_CS_BOUNDARY_32BIT HAL_XSPI_CS_BOUNDARY_64BIT HAL_XSPI_CS_BOUNDARY_128BIT HAL_XSPI_CS_BOUNDARY_256BIT HAL_XSPI_CS_BOUNDARY_512BIT HAL_XSPI_CS_BOUNDARY_1KBIT HAL_XSPI_CS_BOUNDARY_2KBIT HAL_XSPI_CS_BOUNDARY_4KBIT HAL_XSPI_CS_BOUNDARY_8KBIT HAL_XSPI_CS_BOUNDARY_16KBIT HAL_XSPI_CS_BOUNDARY_32KBIT HAL_XSPI_CS_BOUNDARY_64KBIT HAL_XSPI_CS_BOUNDARY_128KBIT HAL_XSPI_CS_BOUNDARY_256KBIT HAL_XSPI_CS_BOUNDARY_512KBIT HAL_XSPI_CS_BOUNDARY_1MBIT HAL_XSPI_CS_BOUNDARY_2MBIT HAL_XSPI_CS_BOUNDARY_4MBIT HAL_XSPI_CS_BOUNDARY_8MBIT HAL_XSPI_CS_BOUNDARY_16MBIT HAL_XSPI_CS_BOUNDARY_32MBIT HAL_XSPI_CS_BOUNDARY_64MBIT HAL_XSPI_CS_BOUNDARY_128MBIT HAL_XSPI_CS_BOUNDARY_256MBIT HAL_XSPI_CS_BOUNDARY_512MBIT HAL_XSPI_CS_BOUNDARY_1GBIT HAL_XSPI_CS_BOUNDARY_2GBIT HAL_XSPI_CS_BOUNDARY_4GBIT HAL_XSPI_CS_BOUNDARY_8GBIT HAL_XSPI_CS_BOUNDARY_16GBIT } hal_xspi_cs_boundary_t;

---

HAL XSPI clock mode

HAL1	HAL2
#define HAL_XSPI_CLOCK_MODE_0 #define HAL_XSPI_CLOCK_MODE_3	typedef enum { HAL_XSPI_CLOCK_LOW HAL_XSPI_CLOCK_HIGH } hal_xspi_clock_polarity_t;

---

HAL XSPI data mode

HAL1	HAL2
#define HAL_XSPI_DATA_NONE #define HAL_XSPI_DATA_1_LINE #define HAL_XSPI_DATA_2_LINES #define HAL_XSPI_DATA_4_LINES #define HAL_XSPI_DATA_8_LINES #define HAL_XSPI_DATA_16_LINES	typedef enum { HAL_XSPI_REGULAR_DATA_NONE HAL_XSPI_REGULAR_DATA_1LINE HAL_XSPI_REGULAR_DATA_2LINES HAL_XSPI_REGULAR_DATA_4LINES HAL_XSPI_REGULAR_DATA_8LINES HAL_XSPI_REGULAR_DATA_16LINES } hal_xspi_regular_data_mode_t;

---

HAL XSPI data DTR mode

HAL1	HAL2
#define HAL_XSPI_DATA_DTR_DISABLE #define HAL_XSPI_DATA_DTR_ENABLE	typedef enum { HAL_XSPI_DATA_DTR_DISABLED HAL_XSPI_DATA_DTR_ENABLED } hal_xspi_data_dtr_status_t;

---

HAL XSPI delay block bypass

HAL1	HAL2
#define HAL_XSPI_DELAY_BLOCK_ON #define HAL_XSPI_DELAY_BLOCK_BYPASS	typedef enum { HAL_XSPI_DLYB_ON HAL_XSPI_DLYB_BYPASS } hal_xspi_dlyb_state_t;

---

HAL XSPI delay hold quarter cycle

HAL1	HAL2
#define HAL_XSPI_DHQC_DISABLE #define HAL_XSPI_DHQC_ENABLE	typedef enum { HAL_XSPI_DELAY_HOLD_NONE HAL_XSPI_DELAY_HOLD_QUARTCYCLE } hal_xspi_delay_hold_t;

---

HAL XSPI DQS mode

HAL1	HAL2
#define HAL_XSPI_DQS_DISABLE #define HAL_XSPI_DQS_ENABLE	typedef enum { HAL_XSPI_DQS_DISABLED HAL_XSPI_DQS_ENABLED } hal_xspi_dqs_status_t;

---

HAL XSPI hyperbus latency mode

HAL1	HAL2
#define HAL_XSPI_VARIABLE_LATENCY #define HAL_XSPI_FIXED_LATENCY	typedef enum { HAL_XSPI_LATENCY_VARIABLE HAL_XSPI_LATENCY_FIXED } hal_xspi_latency_mode_t;

---

HAL XSPI free running clock

HAL1	HAL2
#define HAL_XSPI_FREERUNCLK_DISABLE #define HAL_XSPI_FREERUNCLK_ENABLE	typedef enum { HAL_XSPI_FREE_RUNNING_CLK_DISABLED HAL_XSPI_FREE_RUNNING_CLK_ENABLED } hal_xspi_free_running_clk_status_t;

---

HAL XSPI instruction width

HAL1	HAL2
#define HAL_XSPI_INSTRUCTION_8_BITS #define HAL_XSPI_INSTRUCTION_16_BITS #define HAL_XSPI_INSTRUCTION_24_BITS #define HAL_XSPI_INSTRUCTION_32_BITS	typedef enum { HAL_XSPI_INSTRUCTION_8BIT HAL_XSPI_INSTRUCTION_16BIT HAL_XSPI_INSTRUCTION_24BIT HAL_XSPI_INSTRUCTION_32BIT } hal_xspi_instruction_width_t;

---

HAL XSPI instruction mode

HAL1	HAL2
#define HAL_XSPI_INSTRUCTION_NONE #define HAL_XSPI_INSTRUCTION_1_LINE #define HAL_XSPI_INSTRUCTION_2_LINES #define HAL_XSPI_INSTRUCTION_4_LINES #define HAL_XSPI_INSTRUCTION_8_LINES	typedef enum { HAL_XSPI_INSTRUCTION_NONE HAL_XSPI_INSTRUCTION_1LINE HAL_XSPI_INSTRUCTION_2LINES HAL_XSPI_INSTRUCTION_4LINES HAL_XSPI_INSTRUCTION_8LINES } hal_xspi_instruction_mode_t;

---

HAL XSPI instruction DTR mode

HAL1	HAL2
#define HAL_XSPI_INSTRUCTION_DTR_DISABLE #define HAL_XSPI_INSTRUCTION_DTR_ENABLE	typedef enum { HAL_XSPI_INSTRUCTION_DTR_DISABLED HAL_XSPI_INSTRUCTION_DTR_ENABLED } hal_xspi_instruction_dtr_status_t;

---

HAL XSPI hyperbus write zero latency activation

HAL1	HAL2
#define HAL_XSPI_LATENCY_ON_WRITE #define HAL_XSPI_NO_LATENCY_ON_WRITE	typedef enum { HAL_XSPI_WRITE_ZERO_LATENCY_ENABLED HAL_XSPI_WRITE_ZERO_LATENCY_DISABLED } hal_xspi_write_zero_latency_status_t;

---

HAL XSPI match mode

HAL1	HAL2
#define HAL_XSPI_MATCH_MODE_AND #define HAL_XSPI_MATCH_MODE_OR	typedef enum { HAL_XSPI_MATCH_MODE_AND HAL_XSPI_MATCH_MODE_OR } hal_xspi_match_mode_t;

---

HAL XSPI hyperbus address space

HAL1	HAL2
#define HAL_XSPI_MEMORY_ADDRESS_SPACE #define HAL_XSPI_REGISTER_ADDRESS_SPACE	typedef enum { HAL_XSPI_ADDR_MEMORY HAL_XSPI_ADDR_REGISTER } hal_xspi_addr_space_t;

---

HAL XSPI memory type

HAL1	HAL2
#define HAL_XSPI_MEMTYPE_MICRON #define HAL_XSPI_MEMTYPE_MACRONIX #define HAL_XSPI_MEMTYPE_APMEM #define HAL_XSPI_MEMTYPE_MACRONIX_RAM #define HAL_XSPI_MEMTYPE_HYPERBUS #define HAL_XSPI_MEMTYPE_APMEM_16BITS	typedef enum { HAL_XSPI_MEMORY_TYPE_MICRON HAL_XSPI_MEMORY_TYPE_MACRONIX HAL_XSPI_MEMORY_TYPE_APMEM HAL_XSPI_MEMORY_TYPE_MACRONIX_RAM HAL_XSPI_MEMORY_TYPE_HYPERBUS HAL_XSPI_MEMORY_TYPE_APMEM_16BIT } hal_xspi_memory_type_t;

---

HAL XSPI operation type

HAL1	HAL2
#define HAL_XSPI_OPTYPE_COMMON_CFG #define HAL_XSPI_OPTYPE_READ_CFG #define HAL_XSPI_OPTYPE_WRAP_CFG #define HAL_XSPI_OPTYPE_WRITE_CFG	typedef enum { HAL_XSPI_OPERATION_COMMON_CFG HAL_XSPI_OPERATION_READ_CFG HAL_XSPI_OPERATION_WRITE_CFG HAL_XSPI_OPERATION_WRAP_CFG } hal_xspi_operation_type_t;

---

HAL XSPI sample shifting

HAL1	HAL2
#define HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE #define HAL_XSPI_SAMPLE_SHIFT_NONE	typedef enum { HAL_XSPI_SAMPLE_SHIFT_HALFCYCLE HAL_XSPI_SAMPLE_SHIFT_NONE } hal_xspi_sample_shift_t;

---

HAL XSPI IO select

HAL1	HAL2
#define HAL_XSPI_SELECT_IO_3_0 #define HAL_XSPI_SELECT_IO_7_4 #define HAL_XSPI_SELECT_IO_11_8 #define HAL_XSPI_SELECT_IO_15_12 #define HAL_XSPI_SELECT_IO_7_0 #define HAL_XSPI_SELECT_IO_15_8	typedef enum { HAL_XSPI_IO_3_0 HAL_XSPI_IO_7_4 HAL_XSPI_IO_11_8 HAL_XSPI_IO_15_12 HAL_XSPI_IO_7_0 HAL_XSPI_IO_15_8 } hal_xspi_io_select_t;

---

HAL XSPI memory mode

HAL1	HAL2
#define HAL_XSPI_SINGLE_MEM #define HAL_XSPI_DUAL_MEM	typedef enum { HAL_XSPI_MEMORY_SINGLE HAL_XSPI_MEMORY_DUAL } hal_xspi_memory_mode_t;

---

HAL XSPI SIOO mode

HAL1	HAL2
#define HAL_XSPI_SIOO_INST_EVERY_CMD #define HAL_XSPI_SIOO_INST_ONLY_FIRST_CMD	typedef enum { HAL_XSPI_SIOO_DISABLED HAL_XSPI_SIOO_ENABLED } hal_xspi_sioo_status_t;

---

HAL XSPI memory size

HAL1

HAL2

#define HAL_XSPI_SIZE_16B #define HAL_XSPI_SIZE_32B #define HAL_XSPI_SIZE_64B #define HAL_XSPI_SIZE_128B #define HAL_XSPI_SIZE_256B #define HAL_XSPI_SIZE_512B #define HAL_XSPI_SIZE_1KB #define HAL_XSPI_SIZE_2KB #define HAL_XSPI_SIZE_4KB #define HAL_XSPI_SIZE_8KB #define HAL_XSPI_SIZE_16KB #define HAL_XSPI_SIZE_32KB #define HAL_XSPI_SIZE_64KB #define HAL_XSPI_SIZE_128KB #define HAL_XSPI_SIZE_256KB #define HAL_XSPI_SIZE_512KB #define HAL_XSPI_SIZE_1MB #define HAL_XSPI_SIZE_2MB #define HAL_XSPI_SIZE_4MB #define HAL_XSPI_SIZE_8MB #define HAL_XSPI_SIZE_16MB #define HAL_XSPI_SIZE_32MB #define HAL_XSPI_SIZE_64MB #define HAL_XSPI_SIZE_128MB #define HAL_XSPI_SIZE_256MB #define HAL_XSPI_SIZE_512MB #define HAL_XSPI_SIZE_1GB #define HAL_XSPI_SIZE_2GB #define HAL_XSPI_SIZE_4GB #define HAL_XSPI_SIZE_8GB #define HAL_XSPI_SIZE_16GB #define HAL_XSPI_SIZE_32GB

typedef enum { HAL_XSPI_MEMORY_SIZE_16BIT HAL_XSPI_MEMORY_SIZE_32BIT HAL_XSPI_MEMORY_SIZE_64BIT HAL_XSPI_MEMORY_SIZE_128BIT HAL_XSPI_MEMORY_SIZE_256BIT HAL_XSPI_MEMORY_SIZE_512BIT HAL_XSPI_MEMORY_SIZE_1KBIT HAL_XSPI_MEMORY_SIZE_2KBIT HAL_XSPI_MEMORY_SIZE_4KBIT HAL_XSPI_MEMORY_SIZE_8KBIT HAL_XSPI_MEMORY_SIZE_16KBIT HAL_XSPI_MEMORY_SIZE_32KBIT HAL_XSPI_MEMORY_SIZE_64KBIT HAL_XSPI_MEMORY_SIZE_128KBIT HAL_XSPI_MEMORY_SIZE_256KBIT HAL_XSPI_MEMORY_SIZE_512KBIT HAL_XSPI_MEMORY_SIZE_1MBIT HAL_XSPI_MEMORY_SIZE_2MBIT HAL_XSPI_MEMORY_SIZE_4MBIT HAL_XSPI_MEMORY_SIZE_8MBIT HAL_XSPI_MEMORY_SIZE_16MBIT HAL_XSPI_MEMORY_SIZE_32MBIT HAL_XSPI_MEMORY_SIZE_64MBIT HAL_XSPI_MEMORY_SIZE_128MBIT HAL_XSPI_MEMORY_SIZE_256MBIT HAL_XSPI_MEMORY_SIZE_512MBIT HAL_XSPI_MEMORY_SIZE_1GBIT HAL_XSPI_MEMORY_SIZE_2GBIT HAL_XSPI_MEMORY_SIZE_4GBIT HAL_XSPI_MEMORY_SIZE_8GBIT HAL_XSPI_MEMORY_SIZE_16GBIT HAL_XSPI_MEMORY_SIZE_32GBIT } hal_xspi_memory_size_t;

---

HAL XSPI timeout activation

HAL1	HAL2
#define HAL_XSPI_TIMEOUT_COUNTER_DISABLE #define HAL_XSPI_TIMEOUT_COUNTER_ENABLE	typedef enum { HAL_XSPI_TIMEOUT_DISABLE HAL_XSPI_TIMEOUT_ENABLE } hal_xspi_timeout_activation_t;

---

HAL XSPI wrap size

HAL1	HAL2
#define HAL_XSPI_WRAP_NOT_SUPPORTED #define HAL_XSPI_WRAP_16_BYTES #define HAL_XSPI_WRAP_32_BYTES #define HAL_XSPI_WRAP_64_BYTES #define HAL_XSPI_WRAP_128_BYTES	typedef enum { HAL_XSPI_WRAP_NOT_SUPPORTED HAL_XSPI_WRAP_16BYTE HAL_XSPI_WRAP_32BYTE HAL_XSPI_WRAP_64BYTE HAL_XSPI_WRAP_128BYTE } hal_xspi_wrap_size_t;

---

HAL XSPI flags

HAL1	HAL2
#define HAL_XSPI_FLAG_BUSY #define HAL_XSPI_FLAG_TO #define HAL_XSPI_FLAG_SM #define HAL_XSPI_FLAG_FT #define HAL_XSPI_FLAG_TC #define HAL_XSPI_FLAG_TE	#define HAL_XSPI_FLAG_BUSY #define HAL_XSPI_FLAG_TO #define HAL_XSPI_FLAG_SM #define HAL_XSPI_FLAG_FT #define HAL_XSPI_FLAG_TC #define HAL_XSPI_FLAG_TE #define HAL_XSPI_FLAG_ALL

---

HAL XSPI interrupts

HAL1	HAL2
#define HAL_XSPI_IT_TO #define HAL_XSPI_IT_SM #define HAL_XSPI_IT_FT #define HAL_XSPI_IT_TC #define HAL_XSPI_IT_TE	#define HAL_XSPI_IT_TO #define HAL_XSPI_IT_SM #define HAL_XSPI_IT_FT #define HAL_XSPI_IT_TC #define HAL_XSPI_IT_TE #define HAL_XSPI_IT_ALL

---

HAL XSPI error codes

HAL1	HAL2
#define HAL_XSPI_ERROR_NONE #define HAL_XSPI_ERROR_TIMEOUT #define HAL_XSPI_ERROR_TRANSFER #define HAL_XSPI_ERROR_DMA #define HAL_XSPI_ERROR_INVALID_PARAM #define HAL_XSPI_ERROR_INVALID_SEQUENCE #define HAL_XSPI_ERROR_INVALID_CALLBACK	#define HAL_XSPI_ERROR_NONE #define HAL_XSPI_ERROR_TIMEOUT #define HAL_XSPI_ERROR_TRANSFER #define HAL_XSPI_ERROR_DMA Removed; These kinds of logical errors are reported by the direct function return

Related concept:

• Revised and optimized HAL error management

---

HAL XSPI timeout definition

HAL1	HAL2
#define HAL_XSPI_TIMEOUT_DEFAULT_VALUE	Moved to the source file as a private constant as it is not intended to be used by the user.

---

HAL XSPI IO port

There are only two available ports, HAL_XSPIM_IOPORT_3 to HAL_XSPIM_IOPORT_8 are not physically present. They were removed in HAL2.

For more details refer to : HAL XSPI IO manager configuration type definition

HAL1

HAL2

#define HAL_XSPIM_IOPORT_NONE #define HAL_XSPIM_IOPORT_1_LOW #define HAL_XSPIM_IOPORT_1_HIGH #define HAL_XSPIM_IOPORT_2_LOW #define HAL_XSPIM_IOPORT_2_HIGH #define HAL_XSPIM_IOPORT_3_LOW #define HAL_XSPIM_IOPORT_3_HIGH #define HAL_XSPIM_IOPORT_4_LOW #define HAL_XSPIM_IOPORT_4_HIGH #define HAL_XSPIM_IOPORT_5_LOW #define HAL_XSPIM_IOPORT_5_HIGH #define HAL_XSPIM_IOPORT_6_LOW #define HAL_XSPIM_IOPORT_6_HIGH #define HAL_XSPIM_IOPORT_7_LOW #define HAL_XSPIM_IOPORT_7_HIGH #define HAL_XSPIM_IOPORT_8_LOW #define HAL_XSPIM_IOPORT_8_HIGH

typedef enum { HAL_XSPI_XSPIM_IO_NONE HAL_XSPI_XSPIM_XSPI1_IO_LOW HAL_XSPI_XSPIM_XSPI1_IO_HIGH HAL_XSPI_XSPIM_XSPI2_IO_LOW HAL_XSPI_XSPIM_XSPI2_IO_HIGH HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_LOW HAL_XSPI_XSPIM_XSPI1_XSPI2_IO_HIGH } hal_xspi_xspim_io_t;

---

HAL XSPI calibration delay type

HAL1	HAL2
#define HAL_XSPI_CAL_FULL_CYCLE_DELAY #define HAL_XSPI_CAL_FEEDBACK_CLK_DELAY #define HAL_XSPI_CAL_DATA_OUTPUT_DELAY #define HAL_XSPI_CAL_DQS_INPUT_DELAY	typedef enum { HAL_XSPI_HSIC_DELAY_CAL_FULL_CYCLE HAL_XSPI_HSIC_DELAY_CAL_FEEDBACK_CLK HAL_XSPI_HSIC_DELAY_CAL_DATA_OUTPUT HAL_XSPI_HSIC_DELAY_CAL_DQS_INPUT } hal_xspi_hsic_delay_cal_type_t;

---

HaaL XSPI calibration maximal value

HAL1	HAL2
#define HAL_XSPI_MAXCAL_NOT_REACHED #define HAL_XSPI_MAXCAL_REACHED	typedef enum { HAL_XSPI_HSIC_MAX_CAL_NOT_REACHED HAL_XSPI_HSIC_MAX_CAL_REACHED } hal_xspi_hsic_max_cal_mode_t;